The invention relates generally to integrated circuits and in particular to a system and a method for determining voltage in a specified location in an integrated circuit chip. Specifically, the invention relates to a voltage measurement system comprising an on-chip voltage measurement device as well as off-chip equipment for generating a reference voltage and probing signals.
Modern high-end integrated circuits (ICs) are known to require constant voltage levels as well as precise and stable clock signals in order to ensure IC functionality. Therefore, supply voltage levels and waveforms, clock shapes etc. are critical items in these high end electronic designs which need to fulfill ambitious requirements with respect to reliability and robustness. As a consequence, voltage drop analysis, voltage stability analysis, clock shape analysis etc. play an important role for the verification and characterization of VLSI chips, especially in devices operating at high clock grid frequencies. In these integrated circuits, an appropriate interpretation of test chip measurements requires an exact knowledge of local voltage and clock levels at various locations within the design. Thus, there is a need for a methodology that is able to verify local voltage levels (e.g. of supply voltage, clock signals etc.) during early VLSI tests, first module tests as well as final compound operation in system environment.
Traditional supply voltage measurement of integrated circuits is performed outside of the chip and makes use of sense lines to bring on-chip signals off the chip for measurement. Once the voltage being tested has been taken off-chip through the chip's I/O pad, this voltage may then be measured using an oscilloscope or multimeter. In order to perform this kind of measurement, however, sense lines need to be physically attached to their pin assignments and therefore reduce the number of free pins available as I/O ports of the chip under consideration. Therefore, this kind of voltage measurement consumes I/O capability and is cost intensive (or not available) when required at multiple locations within a chip. Moreover, as the voltage is taken off-chip, the chip's package may introduce parasitic effects such as parasitic capacitance. If the voltage to be tested is of high impedance, the integrity of the signal may not be able to withstand the parasitic effects of the I/O ports and the package, so that the voltage cannot be measured accurately with an external oscilloscope of multimeter.
The impedance issue may be overcome by means of a driver (such as an amplifier). The amplified signal is taken off-chip via the chip's I/O ports and package and fed into an oscilloscope or multimeter for analysis. While this arrangement allows measurement of on-chip voltage signals, there is still the problem of noise and losses originating from the I/O pad and chip package.
It is also possible to implement on-chip A/D converters which enable on-chip measurement of analog voltages: The A/D converter translates the analog voltage level to a digital value based on a conversion with respect to a reference voltage, and the digital value is stored in logic located on the chip. While the use of on-chip A/D converters increases measurement accuracy since the analog signal is not taken off the chip, it is costly because it requires extra logic (and thus silicon area) and adds complexity to the system. In an effort to overcome this problem, International Publication No. WO2006/119303A2, entitled “Apparatus and Methods for Measurement of Analog Voltages in an Integrated Circuit,” Fung et al., published Nov. 9, 2006, which is hereby incorporated herein by reference in its entirety, discloses an on-chip measurement device which comprises a D/A converter for generating an analog voltage and a comparator for comparing this analog voltage to a reference voltage provided on-chip. The output of the comparator is fed into a sequential logic. The measurement device described in WO 2006/119303 A2 may be capable of accurate on-chip voltage level measurements, but it does not allow measurements with a high time resolution which are needed for assessing noise associated with certain activities executing within the chip and/or clock signal properties.
U.S. Publication No. 2009/0072810A1, entitled “Voltage-Drop Measuring Circuit, Semiconductor Device and System Having the Same, and Associated Methods,” Lee et al., published Mar. 19, 2009, which is hereby incorporated herein by reference in its entirety, discloses an on-chip voltage-drop measuring circuit which is capable of measuring a voltage drop caused by a shunt resistance component as part of a power line. The voltage-drop measuring circuit comprises a sensing circuit with sensors configured to generate a sensing voltage received by the sensor from a power pad through a power line between the sensor and the power pad. While this measuring circuit may be capable of detecting power drops within the chip, it generates the reference voltage from the VDD supply voltage of the chip and thus influences voltage levels within the chip. Moreover, the measuring circuit does not provide the high temporal resolution required to analyze local VDD noise of clock shapes.
U.S. Publication No. 2010/0109700A1, entitled “On-Chip Detection of Power Supply Vulnerabilities,” Ferraiolo et al., published May 6, 2010, which is hereby incorporated herein by reference in its entirety, describes an on-chip sensor for detecting power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring off-chip components.
U.S. Publication No. 2003/0052331A1, entitled “Analog-Based Mechanism for Determining Voltage,” Gauthier et al., published Mar. 20, 2003, which is hereby incorporated herein by reference in its entirety, shows an on-chip voltage sensor geared at selectively eliminating noise from a voltage measurement. The on-chip voltage sensor has resistive and capacitive components in the voltage divider, thus allowing a voltage on a section of the chip to be measured exclusive of high-frequency noise
Additional on-chip devices for measuring voltage in an integrated circuit chip are disclosed in U.S. Publication No. 2008/0249727A1, entitled “Systems and Methods for Determining Variations in Voltages Applied to an Integrated Circuit Chip,” Takase, published Oct. 9, 2008; U.S. Publication No. 2010/0176873A1, entitled “Internal Voltage Generator for Semiconductor Integrated Circuit Capable of Compensating for Change in Voltage Level,” Jul. 15, 2010, published Jul. 15, 2010; U.S. Publication No. 2004/0128115A1, entitled “Hierarchical Power Supply Noise Monitoring Device and System for Very Large Scale Integrated Circuits,” Chen et al., published Jul. 1, 2004; and U.S. Pat. No. 7,355,429B2, entitled “On-Chip Power Supply Noise Detector,” Jenkins et al., issued Apr. 8, 2008, each of which is hereby incorporated herein by reference in its entirety.
While the devices described are capable of voltage measurement within the chip under consideration, there is still a need for a simple and efficient methodology for accurate high-speed voltage measurements within an integrated circuit. In particular, the methodology should be capable of yielding supply voltage and clock shape measurements; more generally, the methodology should enable high-speed measurements of time domain voltage waveforms within the chip. Moreover, this methodology should require as little chip resources (such as chip area, chip input and output ports) as possible.